In the basic machine cycle the CAPC1 processor performs Fetch Operation in the first 4 subcyles, C0 to C3. At the last subcycle C3 of Operation, a machine instruction in the form of 16 bit word is copied into the Instruction Register which is the center piece of the Execution Unit of CAPC1. The OP(eration) code, codeBit 15, 14, 13, and 12 of the machine instruction in IR is decoded immediately to identify and execute the instruction in the last 4 subcycles, C4 to C7. Each output pin from Machine Instruction Decoder represents the corresponding machine instruction and be wired to a set of registers by control lines derived from the clock subcycles C4 to C7.

We now look at the wiring of machine instruction LDG. The upper 4 bit is "0110", the OP(eration) code. The lower 12 bit Operand points to a memory location of the next machine instruction.