| (1a) | Describe in general terms what is the above micro program and its functions.
|
| * | A 16 bit Macro Instruction Code is fetched (into IR), decoded and executed
- repeatedly in a permanent loop. |
| (1b) | Mark clearly the unit where this micro program is stored in the block diagram in the last exam page.
|
| * | In the 256x32 Control Store box. |
| (1c) | Write the corresponding 32 bit micro code for the micro assembly language instruction
"tir:=lshift(tir+ir); if N then goto 25;":
|
| * |
| Bit | 31 | 30,29 |
28,27 | 26,25 | 24 |
23 | 22 | 21 |
20 | 19,18,17,16 | 15,14,13,12 |
11,10,9,8 | 7,6,5,4,3,2,1,0 |
| Signal | AMUX | COND |
ALU | Shift | MBR |
MAR | RD | WR |
ENC | C Bus | B Bus |
A Bus | ADDR |
| 0 | 01 |
00 | 10 | 0 |
0 | 0 | 0 |
1 | 0100 | 0011 |
0100 | 00011001 |
|
| (1d) | What are the contents of PC and TIR registers after the execution of the above micro instruction
if "PC=0F2A, IR=E22C, TIR=FFF0" before the execution ?
|
| * | PC=0F2A, TIR=C438 |
| (1e) | How many cycles of Level 0 machine needed to fetch, decode and execute the macro instruction "DESP 5D" ?
Write down the path (a series of the line numbers in (1)) of micro instructions to perform this operation.
|
| * | 13 cycles : [Fetch]0,1(,2)[Decode]2,28,40,46,50,65,73[Execute]76,77,78,75 |
| (1f) | What is SMASK register in Level 1 Machine ? |
| * | It is one of sixteen 16 bit registers of Level 1 machine.
It provides a mask [MASK=0000000011111111] for the operand (8 bit Stack address offset) of Macro Instructions INSP ans DESP (see line 74 and 76). |
| (1g) | This micro machine is said to be horizontal rather than vertical.
Describe in detail horizontal and vertical machines.
|
| * | In horizintal machines, each bit of most of the Micro Instruction (structure bits)
represents the corresponding control signal (without decoders). In vertical machines, the Micro Instruction structure is
composed of highly encoded fields (of bits). |
| (1h) |
Describe in detail the control signals coming from the Clock Subsystem of Level 0 machine in the diagram.
|
| * | (....) |
| (2) | Study closely the block diagram of Tanenbaum's Machine in the last page.
|
| (2a) |
Describe precisely the input lines of the box called "Micro seq. logic" in the diagram (from Level 1 machine and MIR register).
|
| * | (....) |
| (2b) |
There is no output line from the box called "Micro seq. logic" in the diagram. Design and draw an output line to the proper unit(s) in the diagram.
|
| * | Connect to Mmux box of the Level0 machine. |
| (2c) |
Design and build a circuit by using basic gates, AND, NOT, and OR, to implement the "Micro seq. logic" box by analyzing the micro program of Tanenbaum's Machine (1), especially, Lines 2 to 5.
|
| * |  |