The following is a Skeletal Processor which assigns (copies) the address of the machine instruction from PC, Program Counter, to MAR, Memory Address Register, in the first subcycle, SC0 and increments one itself (PC+1->PC) in the second subcycle, SC1. In order to study for details, click each unit in the design.

(1) Here is an alternate design to wire the component units in a more organized manner. This is done by using a PLA device.

(2) Here is an alternate design to wire the component units in a more organized manner. This is done by making use of a Control Bus. This (or similar) approach has been taken by my students, Peter Hsu, Louis Johannson, and others.

(3) Submit your successful Enhanced PC and Skeletal Processor (Step 2) design (relevant .CCT files) to Dr. Hasegawa by February 6, 10:00pm