LogicWorks 4 Experiments Menu

Laboratory Experiment A

(A) Arbitrator Design/Build an unit in LogicWorks 4/5 according to the following requirements:
(1a) There are at most four skeletal processors on the LogicWorks design sheet,
each with its own clock speed, input line attached to ResetPC and output line to "Carry".
(2b) The Arbitrator box will control the input to the shared resource (as a simple
example, consider a counter which enumerates the number of positive input signals
from all four skeletal processors).
(2c) In this simple design, the Arbitrator box will prevent the other processors' access
when the positive input signal from one processor is being processed by the shared unit.
(2d) When the Arbitrator receives an input from one of four input ports, it checks
whether its own Flag bit is set("1") or not. If it is, then encode the input port number,
clear the Flag and send the signal through Output port as well as its port number.
(2e) After the shared unit completes the processing, set Flag back to 1. In this simple case,
there is no need for waiting (the shared unit to finish processing) time to be considered.

The following is an example design with a number of debugging tools still being attached,
binary displays, binary switches, hex keyboards, and hex displays.

(3) Complete the design of the shared unit (2b) according to the following requirements:
By using the unit built in (2b) as a front end processing unit, the main (5th) skeletal processor
records the number (00..11) of the unit which sent the signal and the time (its own current 12
bit PC value) in the RAM (14 bits) at the memory location pointed by the counter (Inc) in
the above design sheet.

(A)	Arbitrator	Design/Build an unit in LogicWorks 4/5 according to the following requirements: (1a) There are at most four skeletal processors on the LogicWorks design sheet, each with its own clock speed, input line attached to ResetPC and output line to "Carry". (2b) The Arbitrator box will control the input to the shared resource (as a simple example, consider a counter which enumerates the number of positive input signals from all four skeletal processors). (2c) In this simple design, the Arbitrator box will prevent the other processors' access when the positive input signal from one processor is being processed by the shared unit. (2d) When the Arbitrator receives an input from one of four input ports, it checks whether its own Flag bit is set("1") or not. If it is, then encode the input port number, clear the Flag and send the signal through Output port as well as its port number. (2e) After the shared unit completes the processing, set Flag back to 1. In this simple case, there is no need for waiting (the shared unit to finish processing) time to be considered. The following is an example design with a number of debugging tools still being attached, binary displays, binary switches, hex keyboards, and hex displays.





		(3) Complete the design of the shared unit (2b) according to the following requirements: By using the unit built in (2b) as a front end processing unit, the main (5th) skeletal processor records the number (00..11) of the unit which sent the signal and the time (its own current 12 bit PC value) in the RAM (14 bits) at the memory location pointed by the counter (Inc) in the above design sheet.